1. Technical Field
This invention relates in general to integrated semiconductor chip timing or clock circuitry and, more particularly, to a digital network for generating an internal clock signal of desired shape from an external clock signal having a variable duty cycle.
2. Description of the Prior Art
Oscillator inputs to integrated circuit chips typically have poor duty cycle resolution, i.e., varying the time within a given clock cycle when the clock signal, for example, drops from a high state (T.sub.on) to a low state (T.sub.off) Often, a commercially available oscillator may have a T.sub.on /T.sub.off ratio per cycle of anywhere from 30/70 to 70/30 for a clock signal rated at 50/50. To eliminate this variation, microprocessor clock generators traditionally divide the input clock frequency to provide the required clock waveform. For example, a symmetrical clock signal can be obtained by dividing the input clock frequency by two, since the period of the input clock signal is assumed constant. To obtain this symmetrical clock signal, however, the resultant frequency is reduced to one-half the input clock frequency. As the performance of microprocessors is pushed to higher and higher frequencies, providing and distributing 2.times. frequency external clocks in a system is becoming increasingly more difficult. By way of example, using the conventional shaping technique it is necessary to drive a chip with a 100 MHz oscillator to operate at 50 MHz with a symmetrical clock signal. This 2.times. requirement can obviously adversely effect circuit cost and performance characteristics as integrated circuit frequencies increase.
A different signal processing approach is described in an article by Miller et al., of Intel Corporation, entitled "High Performance Circuits for the i486.TM. Processor," Proc. Custom Integrated Circuit Conference, Oct. 2-4, 1989, pp 188-192. This shaping approach uses a 1.times. clock input circuit to ease the timing requirements of the above-described 2.times. signal dividing technique. In the described approach, the duty cycle (or T.sub.on /T.sub.off ratio) for the 1.times. circuit clock signal follows the duty cycle of the input clock signal. Performance of the processor clock generator is maintained by use of a regulator circuit to adjust the internal clock duty cycle independently of the input clock pulse width. Although providing a 1.times. clock signal, the clock regulator uses current mirror transistors and an overlap detector, both of which include charging capacitors which are sensitive to process parameters such as temperature and voltage. Further, this 1.times. clock generator circuit only operates within a limited frequency range. If the input frequency varies sufficiently for any reason, then the circuit will fail to operate.
Thus, there is a genuine need in the art for a process independent digital clock shaping network capable of generating, for example, a 1.times. symmetrical clock signal from an input clock signal have a variable T.sub.on /T.sub.off ratio per cycle.